As the operating frequency of a semiconductor memory device increases, an operating speed inside the semiconductor memory device may be reduced and only an operating frequency of an output portion thereof may be increased, using 2-bit, 4-bit, 8-bit or higher prefetch techniques. Thus, an output multiplexing circuit, which serially transfers internal parallel data to an output terminal, may be installed between the semiconductor memory device and the output portion thereof.
For example, in the case of using a 2-bit prefetch technique, in a Double Data Rate (DDR) synchronous memory device that operates at a speed of, for example, 200 Mbps, an internal core circuit may operate at a frequency of, for example, 100 MHz, whereas double data is transferred in parallel to the multiplexing circuit. The multiplexing circuit serially transfers the double data to an output terminal at rising and falling edges of a clock signal. That is, when using a 2-bit prefetch technique, a 2-to-1 multiplexing circuit may be used.
As an operating frequency of a synchronous memory device increases, in general, a 4-bit, an 8-bit or higher prefetch technique may be applied to the synchronous memory device, so as to reduce an operating frequency inside the synchronous memory device. In this case, a 4-to-1, an 8-to-1 or higher multiplexing circuit may be used. An output multiplexing technique for a double data rate (DDR) synchronous memory device is disclosed in U.S. Pat. No. 6,337,830 B1.
FIG. 1 illustrates a conventional output multiplexing circuit, and FIG. 2 is an operational timing diagram to illustrate operation of the circuit shown in FIG. 1. In this case, a 4-bit prefetch technique is assumed.
Referring to FIG. 1, the conventional output multiplexing circuit includes a plurality of first switch groups 101, 102, 103, and 104, each of which comprises four first switches S101, S102, S103, and S104, a plurality of latch groups 111, 112, 113, and 114, each of which comprises four latches L101, L102, L103, and L104, and a plurality of second switch groups 121, 122, 123, and 124, each of which comprises four second switches S111, S112, S113, and S114.
The first switches S101, S102, S103, and S104 transfer 4-bit data DO_F0, DO_S0, DO_F1, and DO_S1, which are transmitted from a memory cell array via a data path, to the latches L101, L102, L103, and L104 in response to corresponding control signals DLi (i is between 0 and n inclusive). Thus, the 4-bit data DO_F0, DO_S0, DO_F1, and DO_S1 is transferred via the first switches S101, S102, S103, and S104, is simultaneously prefetched into the latches L101, L102, L103, and L104.
The control signals DLi are sequentially activated when the memory device performs a burst operation or data read commands are input into the memory device without a gap. As such, a plurality of data that are consecutively transferred via data paths, are stored in different latch groups.
The second switches S111, S112, S113, and S114 sequentially transfer data stored in the latches L101, L102, L103, and L104 to a node NODE1 in response to signals CDQi_F0, CDQi_S0, CDQi_F1, and CDQi_S1 (i=0, 1, 2, 3, . . . ) that are sequentially activated. CDQi_F0, CDQi_S0, CDQi_F1, and CDQi_S1 are signals that receive Column Address Strobe (CAS) latency information and are sequentially activated.
FIG. 2 is an operational timing diagram illustrating operations of the conventional circuit of FIG. 1. More particularly, FIG. 2 illustrates a clock signal CLK, control signals DL0 and DL1, and sequentially activated CAS latency information signals CDQ0_F0, CDQ0_S0, CDQ0_F1, CDQ0_S1, CDQ1_F0, CDQ1_S0, CDQ1_F1, CDQ1_S1. FIG. 2 also shows output signal DOUT, which is output at output terminal DQ.
In a conventional output multiplexing circuit as described above, as the CAS latency information increases, a parasitic capacitance of the node NODE 1 may increase. As such, it may be difficult to perform high-frequency operations. Moreover, when an operating frequency increases, CAS latency generally increases. In the case of a memory device having CAS latency of 10, i may be 5, and the number of CDQi lines may be 20. All of the CDQi lines may be input into respective output terminals DQ of an output driver 131. The output driver 131 may be controlled in response to an output enable signal PTRST and an inverted output enable signal PTRSTB. Thus, in the case of a wide output terminal DQ (e.g., x16 or x32), the area of a chip may increase due to CDQi line routing.
In addition, skew of a CDQi signal at each output terminal DQ may cause DQ skew, i.e., skew between data output to the output terminal DQ. Thus, each CDQi line may be routed using a skew removal method, such as an H-tree method. As a result, the area of the chip may further increase, and in the case of the wide output terminal DQ, it may be difficult to completely reduce the DQ skew.